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myfixfone


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    Bb5 Information Chips

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    Registration date : 30/08/2008

    Bb5 Information Chips Empty Bb5 Information Chips

    ตั้งหัวข้อ by Webmaster Fri Oct 10, 2008 11:48 am

    RAP3G

    RAP3G is a 3G Radio Application Processor
    Successor for TIKU (used in NOKIA 7600) with some technical improvements and additional features
    In general RAP3G consists of three separate parts:
    Processor subsystem (PSS) that includes ARM926 MCU as a main processor, Lead3 PH3 DSP and related functions
    MCU peripherals
    DSP peripherals
    RAP3G is running with NOS and takes care of all cellular modem activities
    RAP3G core voltage (1.40V) is generated from TAHVO VCORE and I/O voltage (1.8V) is from RETU VIO. Core voltage in sleep mode is lowered to 1.05V

    RETU

    RETU is the primary EM ASIC including following functional blocks:
    Start up logic and reset control
    Charger detection
    Battery voltage monitoring
    32.768kHz clock with external crystal
    Real time clock with external backup battery
    SIM card interface
    Stereo audio codecs and amplifiers
    A/D converter
    Regulators
    Vibra interface
    Digital interface (CBUS)
    RETU ASIC does not include security functions such as UEM(E,K)

    TAHVO

    TAHVO is the secondary EM ASIC including following functional blocks:
    Core supply generation (VCORE & VCOREA)
    Charge control circuitry
    Level shifter and regulator for USB/FBUS
    Current gauge for battery current measuring
    External LED driver control interface
    Digital interface (CBUS)
    TAHVO ASIC does not include security functions such as UEM(E,K)

    CMT Flash
    CMT Flash memory is used to store:
    MCU program code
    DSP program code
    Tuning values
    Certificates
    Capacity: 64Mbit
    Logic and supply voltage for NOR Flash is supplied from VIO (1.8V)
    Flash clock is 48MHz (192MHz/4)

    CMT SDRAM

    CMT SDRAM is mainly used as a dynamic data storage for MCU data
    Capacity: 64MBit
    SDRAM core voltage (1.8V) is generated by RETU’s VDRAM regulator
    I/O voltage (1.8V) is generated by RETU’s VIO regulator
    SDRAM clock is 96MHz (192MHz/2)

    OMAP 1710

    OMAP is the application processor running with Symbian operating system (EPOC)
    Platform for executing all user related application. Main interfaces:
    Camera interface
    Display interface
    Bluetooth interface
    MMC interface
    USB interface
    Keyboard interface
    X-Bus for communication with RAP3G
    OMAP is a standard ASIC designed by Texas Instruments and used also by other manufacturers of mobile phones and handheld PCs
    Core voltage VCORE=1.4V is generated by discrete SMPS, and is lowered to 1.09V in sleep mode
    I/O voltage VIO=1.8V is generated by RETU

    APE Combo Memory

    APE Flash is used to store application code and user data
    It is not possible to execute code directly from Flash -> executables need first to be loaded to DDR and run from there
    Capacity: 256Mbit (Flash), 256Mbit (DDR)
    Core voltage for DDR is VDRAM 1.8V
    VIO 1.8V is for DDR I/O voltage
    Both NAND core and I/O voltages are generated by RETU
    DDR clock is 110MHz (220MHz/2)
    Flash interface speed is 22MHz


    Product Specific Circuitries

    Front Camera

    The front camera is controlled and its data is collected by OMAP
    The I/O voltage of OMAP is 1.8V, and the one of the camera is 2.8V; therefore a level shifter is needed
    The camera is powered with two different voltages from LDO (Low-dropout voltage) regulators:
    VCAM 1.5V for camera digital circuits, and sensor A/D-converter
    VCAM2 2.8V for camera I/O, and sensor photo diode

    Back Camera

    Connected to OMAP via data and control interfaces
    Data transfer: through differential serial interface using clock and data
    Camera control: bidirectional control interface compatible with I2C standard using SCL&SDA signals (1.8V)
    Camera digital voltage is VCAM (1.5V) from discrete LDO
    Camera ****og voltage is VAUX (2.5V) from RETU
    Additional control signals
    Vctrl: high (1.8V)=camera active low (0V)=camera inactive
    ExtCLK: clock from OMAP1710 (9.6MHz)

    Camera Flash Light

    Designed to give more light when taking pictures in dark environment
    The same LED is also used as an indicator light for indicating when:
    a video clip is being recorded
    a picture is taken
    TK1189 is the SMPS for FLED. The enable of TK1189 is controlled by two hosts:
    flash mode is controlled by the camera
    indicator mode is controlled by OMAP

    Bluetooth

    Single chip BT BC3 (includes RF, BB & ROM memory)
    UART interface for control/data with OMAP
    PCM interface for audio data with RAP3G
    IO voltage 1.8V from VIO
    ****og voltage 2.85V from VBAT through discrete LDO
    Clock 38.4MHz from RF part

    Ambient Light Sensor

    Ambient Light Sensor is located in the upper part of the phone and consists of:
    Light guide (part of front cover)
    phototransistor + resistor
    NTC + resistors
    RETU
    Information of ambient lighting is used to control backlights of the phone:
    Keypad lighting is only switched on when environment is dark/dim
    Display backlights are dimmed, when environment is dark/dim

    MMC Interface

    Reduced size MMC can be used to store photos, videos, etc…
    MMC is connected to OMAP
    Interface voltage level is 1.8V and power supply from RETU VSIM2
    EMC protection by using ASIPs (Application Specific Integrated Passive)
    MMC is powered down when MMC cover is opened
    Cover lid open = signal connected to GND
    Cover lid closed = signal connected to 1.8V

    Power Control Loop – WCDMA Transmitter 1/2

    TXC is used to drive the VGA which is used as the “main power controller”
    The PA outside is just for the final setting of the outgoing power
    WCDMA uses closed loop SW power control, where the Base Station will provide information for the terminal to increase or decrease its power by 1 or 2 dB steps

    Power Detection: It is required that terminal must be able to measure its output power in high power level. The power detector measure it and fed a voltage (WTXDET) back to RETU to undergo AD conversion
    Output power needs to be limited to +21 dBm

    Isolator: It passes RF power only in one direction. Without it, RF power may leak in and affect the output of the detection circuit, resulting in error in the power control

    Power Control Loop – WCDMA Transmitter 2/2

    SMPS: The supply voltage of the PA and limits the lowest supply voltage to 1.5V. At highest power levels the SMPS output settles nominally to 3.2V
    The supply voltage and the reference current lines (DAC 101 and DAC 201) are used to set the PA to distortion-free gain according to PA vendor's specification; this is essential in WCDMA

    Phase Lock Loop PLL

    The output of the phase det depend on the phase of the measured frequency compared to the phase of the reference frequency
    PLL charge pump charges or discharges the integrated capacitor in the loop filter based on the output of the phase det (comparator)

    Key Components 0f WCDMA Receiver
    Why do we need Additional Filtering?
    This SAW filter is to attenuate the Tx signal which is leaking through the duplex filter and amplified by the LNA
    Why do we use duplexer instead of antenna switch?
    This is because Tx and Rx are functioning in continuous mode in WCDMA
    What is the use of AGC stage?
    This stage is used to maintain the voltage swing at the AD converter in BB at an adequate level

    Power Control Loop – GSM Transmitter

    Power Detector Circuitry in PA gives a DC value proportional to the output power
    DC level is feedback to the negative input of ERROR amplifier in VINKU
    The DC level is then compare with the TXC reference signal
    The output of the ERROR amplifier is then fed to a buffer amplifier which drive the VGA

    Note: TXC is obtained from the
    network for power level control

    Interfaces to BB

    Supply voltages
    VBATT from battery
    VXO, VCP1, VCP2, VREF from RETU
    Control signals
    AFC, TXC from RETU
    RFBUS from RAP3G
    Data signals
    RXI/Q to RAP3G
    TXI/Q from RAP3G
    Outgoing signals
    Clock (balanced) to RAP3G
    Clock (single ended) to Bluetooth™
    VREF for RXI/Q ADCs
    IREF for TXI/Q DACs
    RFTEMP, WTXDET to RETU

    X-BUS or SSI

    SSI = Speed Serial Interface
    CMT-APE: A communication interface between RAP3G and OMAP1710 using Speed Serial Interface (SSI)
    Data is transmitted via two lines: Data and Flag
    Ready: indicates to opposite side that new frame can be sent
    Wake: activated when data is wanted to transmit to opposite side


    Cracdit By: Jay'Treze
    JaY'TreZe
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    hodda


    จำนวนข้อความ : 1
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    Registration date : 22/10/2008

    Bb5 Information Chips Empty Re: Bb5 Information Chips

    ตั้งหัวข้อ by hodda Fri Nov 28, 2008 1:36 am

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